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227-0116-00L 6 Credits BSC , MSC D-ITET , D-INFK , D-ERDW , D-MAVT , D-MATH , D-PHYS
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VLSI 1: HDL Based Design for FPGAs

Lecturers & Examiners: Frank Kagan Gürkaynak, Prof. Dr. Luca Benini
VVZ CR 4.53

Last Updated: 2026-06-01 11:31:01

Abstract

This first course in a series that extends over three consecutive terms is concerned with tailoring algorithms and with devising high performance hardware architectures for their implementation as ASIC or with FPGAs. The focus is on front end design using HDLs and automatic synthesis for producing industrial-quality circuits.

Objective

Understand Very-Large-Scale Integrated Circuits (VLSI chips), Application-Specific Integrated Circuits (ASIC), and Field-Programmable Gate-Arrays (FPGA). Know their organization and be able to identify suitable application areas. Become fluent in front-end design from architectural conception to gate-level netlists. How to model digital circuits with SystemVerilog. How to ensure they behave as expected with the aid of simulation, testbenches, and assertions. How to take advantage of automatic synthesis tools to produce industrial-quality VLSI and FPGA circuits. Gain practical experience with the hardware description language SystemVerilog and with industrial Electronic Design Automation (EDA) tools.

Content

This course is concerned with system-level issues of VLSI design and FPGA implementations. Topics include: - Overview on design methodologies and fabrication depths. - Levels of abstraction for circuit modeling. - Organization and configuration of commercial field-programmable components. - FPGA design flows. - Dedicated and general purpose architectures compared. - How to obtain an architecture for a given processing algorithm. - Meeting throughput, area, and power goals by way of architectural transformations. - Hardware Description Languages (HDL) and the underlying concepts. - SystemVerilog - Register Transfer Level (RTL) synthesis and its limitations. - Building blocks of digital VLSI circuits. - Functional verification techniques and their limitations. - Modular and largely reusable testbenches. - Assertion-based verification. - Synchronous versus asynchronous circuits. - The case for synchronous circuits. - Periodic events and the Anceau diagram. - Case studies, ASICs compared to microprocessors, DSPs, and FPGAs. During the exercises, students learn how to model FPGAs with SystemVerilog. They write testbenches for simulation purposes and synthesize gate-level netlists for FPGAs. Commercial EDA software by leading vendors is being used throughout.

Resources

Lecture Notes

Textbook and all further documents in English.

Literature

H. Kaeslin: "Top-Down Digital VLSI Design, from Architectures to Gate-Level Circuits and FPGAs", Elsevier, 2014, ISBN 9780128007303.

Learning Materials (Links)

General Information

Language
English
Levels
BSC , MSC
Frequency
Yearly recurring

Examination

Type
session examination
Mode
written 180 minutes
Aids
Student's own hand-written summary, 6 single-sided A4 papers. No electronic help, no photocopies or printouts of any form, for summary preparation. No calculators or communication devices.
Pruefungsaufgaben werden in Englisch vorgegeben, Antworten auf Deutsch oder Englisch akzeptiert.

Course Components

Type Title Time & Place Hours
lecture with exercise VLSI 1: HDL Based Design for FPGAs
  • Tue 08:15-10:00 (ETF C 1)
  • Tue 13:15-16:00 (ETZ D 61.1)
  • Tue 13:15-16:00 (ETZ D 61.2)
  • Tue 13:15-16:00 (ETZ D 96.1)
  • Wed 13:15-16:00 (ETZ D 61.1)
  • Wed 13:15-16:00 (ETZ D 61.2)
  • Wed 13:15-16:00 (ETZ D 96.1)
5 h weekly

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